1. Field of the Invention
The present invention relates to a read circuit technique used for example in a rewritable semiconductor memory device provided with a redundant capacity in which an excessive electric current consumption in a data bus and a sense amplifier is controlled and suppressed so that overall electric current consumption is reduced.
2. Prior Art
In recent years, with the rise of environmental consciousness and the progress in portable electronic devices, the use of memory products having a low electric current consumption is growing. Nevertheless, the electric current consumption in an output data bus and a sense amplifier section tends to increase with increasing bit width and read speed. Thus, reduction is desired in such electric current consumption.
In a large capacity semiconductor memory device requiring a redundant capacity, in order that the influence of degradation in the read speed caused by redundancy replacement should be avoided, a redundancy replacement method with respect to bit configuration is effective. Further, for the purpose of reduction of the electric current consumption in the output data bus and the sense amplifier section, a timing control method is effective that employs a circuit called a dummy circuit or a replica circuit.
In a prior art configuration, a semiconductor memory device of this type comprises a dummy memory cell, a dummy bit line, and a dummy amplifier, so that timing control is performed using a read signal of the dummy amplifier (see, for example, Patent Document 1).
FIG. 6 is a block diagram showing an overall configuration of a prior art semiconductor memory device that has an external bit configuration specification of ×4 and an internal bit configuration of ×5 including redundancy and comprises a dummy circuit for timing control.
In FIG. 6, numeral 1 indicates a memory cell array. The memory cell array 1 comprises memory cell blocks 1a–1d, a redundant memory cell block 1e, and a dummy memory cell block 1f each of which is constructed from a plurality of word lines, a plurality of bit lines, and memory cells arranged at these nodes in the form of a matrix.
Numeral 2 indicates a column gate array. The column gate array 2 includes column gate blocks 2a–2d, a redundant column gate block 2e, and a dummy column gate block 2f. 
Numeral 3 indicates a sense amplifier array. The sense amplifier array 3 includes sense amplifier blocks 3a–3d, a redundant sense amplifier block 3e, and a dummy sense amplifier block 3f. 
Numeral 4 indicates an address buffer for receiving an address 13. Numeral 5 indicates a row decoder for receiving a row address 14 from the address buffer 4. Numeral 6 indicates a column decoder for receiving a column address 15 from the address buffer 4. Numeral 8 indicates a read data bus comprising read data lines 8a–8e and an output enable signal line 19. Numeral 9 indicates an output buffer. Numeral 10 indicates an output data bus comprising output data lines 10a–10d. Numeral 11 indicates a redundant block. Numeral 12 indicates a dummy block. Numeral 16 indicates a sense amplifier control signal bus. Numeral 17 indicates a sense amplifier activation signal line for inputting a sense amplifier activation signal SE. Numeral 18 indicates a redundancy discrimination signal bus.
Here, each unit composed of a memory cell block, a column gate block, and a sense amplifier block is defined as a block. The redundant memory cell block 1e, the redundant column gate block 2e, and the redundant sense amplifier block 3e constitute a redundant block 11. The dummy memory cell block 1f, the dummy column gate block 2f, and the dummy sense amplifier block 3f constitute a dummy block 12.
The redundant block 11 has a memory capacity smaller than or equal to that of the other blocks. Further, the dummy block 12 has a memory capacity smaller than that of the other blocks. The read data lines 8a–8e for outputting read data Da–De and the redundancy discrimination signal bus 18 for inputting a redundancy discrimination signal NRED for selecting the permission or inhibition of output of the read data Da–De to the outside are connected to the output buffer 9. The read data line of the dummy block 12, that is, the output enable signal line 19, is also connected to the output buffer 9. An output enable signal OE is provided through the output enable signal line 19 to the output buffer 9.
The address buffer 4 is connected to the row decoder 5 and the column decoder 6 such that a row address 14 and a column address 15 should be provided to the row decoder 5 and the column decoder 6, respectively.
The redundancy discrimination signal bus 18 for inputting a redundancy discrimination signal NRED comprises, specifically, five signal lines for inputting five signals consisting of a redundancy discrimination signal NREDa through a redundancy discrimination signal NREDe. In the case of no redundancy relief, the redundancy discrimination signal NREDe is solely at an L level, while the other four redundancy discrimination signals NREDa–NREDd are set at an H level. After the redundancy relief, in the block serving as an object of relief, the corresponding redundancy discrimination signal NREDx (x represents any one of a–d) is solely at an L level, while the other four redundancy discrimination signals NREDy (y represents a–d other than x) are set at an H level. The output buffer 9 outputs to the outside the read data of such a blocks each of which have the redundancy discrimination signals of H level among the redundancy discrimination signals NREDa–NREDe.
FIG. 7 is a circuit diagram showing a detailed configuration of the memory cell block 1a, the column gate block 2a, and the sense amplifier block 3a of FIG. 6.
In FIG. 7, numeral 30 indicates a nonvolatile memory cell. Numeral 31 indicates a word line WLn representing a plurality of word lines. Numeral 32 indicates a bit line BLn representing a plurality of bit lines. Numeral 33 indicates a column gate transistor for selecting a bit line BLn. Numeral 34 indicates a column gate selection line YGn for selecting a column gate transistor 33. Numeral 35 indicates a differential amplifier circuit. Numerals 38 and 39 indicate bit line potential generation circuits. Numeral 42 indicates a reference memory cell.
The nonvolatile memory cell 30 is selected from among a plurality of nonvolatile memory cells by the word line WLn and the column gate selection line YGn, and thereby electrically connected to a node 45. NMOS transistors 40 and 41 are connected to nodes 45 and 46 as well as to a data line DLa indicated by numeral 47 and a reference data line DLrefa indicated by numeral 48. The drain of a discharging transistor 49 is connected to the node 45. The data line 47 and the reference data line 48 are connected to the inputs of the differential amplifier circuit 35. The row decoder 5 and the memory cell block 1a are interconnected through a plurality of word lines including the word line WLn. The column decoder 6 and the memory cell block 2a are interconnected through a plurality of column gate lines including the column gate selection line YGn.
The dummy block has the same configuration as FIG. 7 except that a fewer bit lines and a fewer column gates are provided. The data line corresponding to the node 47 is denoted by DLf, while the reference data line corresponding to the node 48 is denoted by DLreff.
The operation of the prior art semiconductor memory device having the above-mentioned configuration is described below with reference to FIGS. 6, 7, and 8.
FIG. 8 is a timing chart for the prior art example shown in FIGS. 6 and 7. The following description is given for the case that the memory cell block 1a serves as an object of read.
First, the address buffer 4 predecodes an address 13 into a row address 14 and a column address 15. Then, the column decoder 6 selects a column gate line YGn as shown in FIG. 8(b).
Then, when a control signal PRE inputted through the signal line 44 in the sense amplifier control signal bus 16 goes to an H level as shown in FIG. 8(c), the bit line potential generation circuits 38 and 39 become activated. Thus, the bit line potential generation circuits 38 and 39 detects the potentials of the nodes 45 and 46 electrically connected respectively to the drain nodes of the nonvolatile memory cell 30 and the reference memory cell 42, and thereby perform feedback to the gate potentials of the NMOS transistors 40 and 41. As a result, the data line DLa indicated by numeral 47 and the reference data line DLrefa indicated by numeral 48 are charged into a certain potential Vi as shown in FIG. 8(e).
Then, as shown in FIG. 8(a), when the row decoder 5 causes the word line WLn to go to an H level, and when the control signal WLref inputted through the signal line 43 in the sense amplifier control signal bus 16 goes to an H level, the nonvolatile memory cell 30 and the reference memory cell 42 which is an NMOS load element are activated. As a result, the nonvolatile memory cell 30 and the reference memory cell 42 begin to reduce the potentials of the nodes 45 and 46.
After a certain time has elapsed, the potentials of the nodes 45 and 46 reach a stable state. At that time, the bit line potential generation circuits 38 and 39 retain the data line DLa and the referenced at a line DLrefa at a potential Voff/Von and a potential Vref, respectively, as shown in FIG. 8(e). Here, the potential Voff and the potential Von correspond respectively to the OFF state and the ON state of the nonvolatile memory cell 30.
Further, the data line DLf and the reference data line DLreff in the dummy sense amplifier block 3f having a configuration similar to FIG. 6 have a potential Vx and a potential Vref, respectively, as shown in FIG. 8(f).
Here, the potential Vx is set up such that the following relations hold for these potentials.|Von−Vref|>|Vx−Vref||Voff−Vref|>|Vx−Vref|Further, in order that these relations should hold in each block, the potential Vx can be adjusted by the layout of the bit line of the dummy memory cell block 1f and by the cell current value of the memory cell. That is, the input potential difference to the differential amplifier circuit of the dummy memory cell block 1f is set to be the minimum among the input potential differences to the differential amplifier circuit of all the blocks.
Then, as shown in FIG. 8(g), when a sense amplifier activation signal SE inputted through the sense amplifier activation signal line 17 goes to an H level, |Von−Vref| or |Voff−Vref| is amplified by the differential amplifier circuit in the sense amplifier block 3a, while |Vx−Vref| is amplified by the differential amplifier circuit in the dummy sense amplifier block 3f. 
Then, read data Da is outputted from the differential amplifier circuit 35 as shown in FIG. 8(h), while read data of the dummy block 12 is outputted as an output enable signal OE from the differential amplifier circuit of the dummy sense amplifier block 3f as shown in FIG. 8(i). The output enable signal OE is data generated by reading the dummy memory cell block having the minimum input potential difference to the differential amplifier circuit, and hence is outputted later than the read data of any other blocks.
Then, as shown in FIG. 8(d), when a control signal DIS inputted through the signal line 50 in the sense amplifier control signal bus 16 goes to an H level, the discharging transistor 49 becomes activated so that the bit line BLn and the node 45 are discharged to the ground potential. Thus, the read operation is completed.
In the case that a variation arises in the load capacitance or the current capability owing to a fabrication variation in the memory cells, the word lines, the bit lines, the data lines, and the differential amplifier circuits, an unstable operation or a malfunctioning occurs during the time after each differential amplifier circuit starts amplifying operation and before a sufficient input potential difference is generated between the data line and the reference data line. This unstable operation or malfunction generates a data uncertainty duration T1 for the read data Da or the other read data Db–De as indicated by numeral 70 in FIG. 8(h).
If the read data were outputted to the outside during the uncertainty duration T1, various problems could arise such as a degradation in the read speed, an increase in the penetration current in the output buffer 9, and an increase in the charge or discharge current of the load capacitance attached to the output data bus. Thus, in order that the transition should occur after the uncertainty duration T1 as shown in FIG. 8(i), the output buffer 9 is controlled by the output enable signal OE having been set to be outputted later than all the read data. As a result, the output buffer 9 is prevented from performing the output operation to the outside in the uncertainty duration T1. As such, as indicated by numeral 71 in FIG. 8(j), the output data DOa–DOd is outputted without an uncertainty duration.
In the output buffer 9, a bus switching operation is performed such that the read data corresponding to blocks having redundancy discrimination signals of H level among the redundancy discrimination signals NREDa–NREDe should be outputted.                Patent Document 1; JP-A No. H8-273365        
However, in the semiconductor memory device employing the prior art read circuit described above, the incorporation of the dummy memory cell block has caused the problem of an increase in the area and the fabrication cost.